A few weeks ago, we’ve seen Apple announce their newest iPhone 13 series devices, a set of phones being powered by the newest Apple A15 SoC. Today, in advance of the full device review which we’ll cover in the near future, we’re taking a closer look at the new generation chipset, looking at what exactly Apple has changed in the new silicon, and whether it lives up to the hype.

This year’s announcement of the A15 was a bit odder on Apple’s PR side of things, notably because the company generally avoided making any generational comparisons between the new design to Apple’s own A14. Particularly notable was the fact that Apple preferred to describe the SoC in context of the competition; while that’s not unusual on the Mac side of things, it was something that this year stood out more than usual for the iPhone announcement.

The few concrete factoids about the A15 were that Apple is using new designs for their CPUs, a faster Neural engine, a new 4- or 5-core GPU depending on the iPhone variant, and a whole new display pipeline and media hardware block for video encoding and decoding, alongside new ISP improvements for camera quality advancements.

On the CPU side of things, improvements were very vague in that Apple quoted to be 50% faster than the competition, and the GPU performance metrics were also made in such a manner, describing the 4-core GPU A15 being +30% faster than the competition, and the 5-core variant being +50% faster. We’ve put the SoC through its initial paces, and in today’s article we’ll be focusing on the exact performance and efficiency metrics of the new chip.

Frequency Boosts; 3.24GHz Performance & 2.0GHz Efficiency Cores

Starting off with the CPU side of things, the new A15 is said to feature two new CPU microarchitectures, both for the performance cores as well as the efficiency cores. The first few reports about the performance of the new cores were focused around the frequencies, which we can now confirm in our measurements:

Maximum Frequency vs Loaded Threads
Per-Core Maximum MHz
Apple A15 1 2 3 4
Performance 1 3240 3180    
Performance 2   3180    
Efficiency 1 2016 2016 2016 2016
Efficiency 2   2016 2016 2016
Efficiency 3     2016 2016
Efficiency 4       2016
Maximum Frequency vs Loaded Threads
Per-Core Maximum MHz
Apple A14 1 2 3 4
Performance 1 2998 2890    
Performance 2   2890    
Efficiency 1 1823 1823 1823 1823
Efficiency 2   1823 1823 1823
Efficiency 3     1823 1823
Efficiency 4       1823

Compared to the A14, the new A15 increases the peak single-core frequency of the two-performance core cluster by 8%, now reaching up to 3240MHz compared to the 2998MHz of the previous generation. When both performance cores are active, their operating frequency actually goes up by 10%, both now running at an aggressive 3180MHz compared to the previous generation’s 2890MHz.

In general, Apple’s frequency increases here are quite aggressive given the fact that it’s quite hard to push this performance aspect of a design, especially when we’re not expecting major performance gains on the part of the new process node. The A15 should be made on an N5P node variant from TSMC, although neither company really discloses the exact details of the design. TSMC claims a +5% frequency increase over N5, so for Apple to have gone further beyond this would have indicated an increase in power consumption, something to keep in mind of when we dive deeper into the power characteristics of the CPUs.

The E-cores of the A15 are now able to clock up to 2016MHz, a 10.5% increase over the A14’s cores. The frequency here is independent of the performance cores, as in the number of threads in the cluster doesn’t affect the other cluster, or vice-versa. Apple has done some more interesting changes to the little cores this generation, which we’ll come to in a bit.

Giant Caches: Performance CPU L2 to 12MB, SLC to Massive 32MB

One more straightforward technical detail Apple revealed during its launch was that the A15 now features double the system cache compared to the A14. Two years ago we had detailed the A13’s new SLC which had grown from 8MB in the A12 to 16MB, a size that was also kept constant in the A14 generation. Apple claiming they’ve doubled this would consequently mean it’s 32MB now in the A15.

Looking at our latency tests on the new A15, we can indeed now confirm that the SLC has now doubled up to 32MB, further pushing the memory depth to reach DRAM. Apple’s SLC is likely to be a key factor in the power efficiency of the chip, being able to keep memory accesses on the same silicon rather than going out to slower, and more power inefficient DRAM. We’ve seen these types of last-level caches being employed by more SoC vendors, but at 32MB, the new A15 dwarfs the competition’s implementations, such as the 3MB SLC on the Snapdragon 888 or the estimated 6-8MB SLC on the Exynos 2100.

What Apple didn’t divulge, is also changes to the L2 cache of the performance cores, which has now grown by 50% from 8MB to 12MB. This was actually the same L2 size as on the Apple M1, only this time around it’s serving only two performance cores rather than four. The access latency appears to have risen from 16 cycles on the A14 to 18 cycles on the A15. 

A 12MB L2 is again humongous, over double compared to the combined L3+L2 (4+1+3x0.5 = 6.5MB) of other designs such as the Snapdragon 888. It very much appears Apple has invested a lot of SRAM into this year’s SoC generation.

The efficiency cores this year don’t seem to have changed their cache sizes, remaining at 64KB L1D’s and 4MB shared L2’s, however we see Apple has increased the L2 TLB to 2048 entries, now covering up to 32MB, likely to facilitate better SLC access latencies. Interestingly, Apple this year now allows the efficiency cores to have faster DRAM access, with latencies now at around 130ns versus the +215ns on the A14, again something to keep in mind of in the next performance section of the article.

CPU Microarchitecture Changes: A Slow(er) Year?

This year’s CPU microarchitectures were a bit of a wildcard. Earlier this year, Arm had announced the new Armv9 ISA, predominantly defined by the new SVE2 SIMD instruction set, as well as the company’s new Cortex series CPU IP which employs the new architecture. Back in 2013, Apple was notorious for being the first on the market with an Armv8 CPU, the first 64-bit capable mobile design. Given that context, I had generally expected this year’s generation to introduce v9 as well, but however that doesn’t seem to be the case for the A15.

Microarchitecturally, the new performance cores on the A15 doesn’t seem to differ much from last year’s designs. I haven’t invested the time yet to look at every nook and cranny of the design, but at least the back-end of the processor is identical in throughput and latencies compared to the A14 performance cores.

The efficiency cores have had more changes, alongside some of the memory subsystem TLB changes, the new E-core now gains an extra integer ALU, bringing the total up to 4, up from the previous 3. The core for some time no longer could be called “little” by any means, and it seems to have grown even more this year, again, something we’ll showcase in the performance section.

The possible reason for Apple’s more moderate micro-architectural changes this year might be a storm of a few factors – Apple had notably lost their lead architect on the big performance cores, as well as parts of the design teams, to Nuvia back in 2019 (later acquired by Qualcomm earlier this year). The shift towards Armv9 might also imply some more work done on the design, and the pandemic situation might also have contributed to some non-ideal execution. We’ll have to examine next year’s A16 to really determine if Apple’s design cadence has slowed down, or whether this was merely just a slippage, or simply a lull before a much larger change in the next microarchitecture.

Of course, the tone here paints rather conservative improvement of the A15’s CPUs, which when looking at performance and efficiency, are anything but that.

CPU ST Performance: Faster & More Efficient
Comments Locked


View All Comments

  • repoman27 - Monday, October 4, 2021 - link

    By 2023 Apple SoCs will likely include integrated 5G, seeing as they spent $1B to acquire Intel’s modem division. Until then, Qualcomm discrete is really their only option.
  • cha0z_ - Tuesday, October 5, 2021 - link

    As said - no integrated modem is entirely doing of qualcomm. Won't last long tho, apple are already deep into designing their own 5G modem ;)
  • 5j3rul3 - Monday, October 4, 2021 - link

    Will anandtech review iPad mini 2021 and iPad Pro 12.9 2021?
  • Andrei Frumusanu - Monday, October 4, 2021 - link

    Currently we have no plans on the iPads, no.
  • 5j3rul3 - Monday, October 4, 2021 - link

    Thank you!
  • name99 - Monday, October 4, 2021 - link

    I would be curious if you at least ran the latency tests on an M1 device, to compare.
    That would allow us to perhaps understand how the L2 is split.

    Right now one can imagine at least three possibilities:
    - drowsy cache with three or four segments (usually you do this by sleeping some fraction of the ways), so that as you go larger some fraction of the time you are hitting a drowsy segment more often and taking an extra cycle

    - virtual L3. ie each core gets half the L2, and some fraction (again likely by way) of the L2 "attached" to the other core is treated as virtual L3

    - your hypothesis for the A13 that some fraction of the L2 was (either absolutely, or effectively in terms of the heuristics used) locked to use by the E cores

    If we has curves for M1 (with 4 rather than 2 P clients) the relative fractions at each size might serve to stengthen vs weaken among these options.
  • Andrei Frumusanu - Monday, October 4, 2021 - link

    We had run latency on M1 when I still had it; https://images.anandtech.com/doci/16252/latency-m1...

    It obviously looks quite different. I've determined before that Apple does some logical partitioning of the caches, it's a bit hard to measure one core while the other does something.
  • name99 - Monday, October 4, 2021 - link

    Thanks for the plot!
    That seems to show jumps at 3MB and 6MB, which does suggest a per-core split (whether logical or physical, who knows; does the question even have any real meaning?).
    I can make up a model for it (each cache gets 3MB of L2, other core's L2 can be used as virtual L2, each of the 3MB is split into three segments that are independently drowsy) which kinda fits what we see, and which one can kinda retrofit to the A14 graph.

    I'm always loathe to blame "energy saving" for weird anomalies; in this case drowsy cache. But it's not a completely crazy hypothesis. On the other hand, we know that the SLC is also drowsy (thought at a rather finer granularity) and yet we don't see an obvious jump signature of drowsiness there (though maybe we wouldn't, given the fine granularity; just a steady ramp in mean access time?)

    I could imagine that the way the split works is something like half the tags, and so half the way's are "allocated" to one core rather than the other. If you find the result in "your" tag lookup, great; if not, lose a cycle and look in the tags of the other core(s)? Would mostly work well, uses lower energy, and you only have to pay the occasional extra tag lookup(s) when you're sharing data or code with another core.

    This would imply that you could see a signature of the effect by investigating how many ways the cache presents. It should appear to present say 4 fast ways and 4 slower ways (or 3 fast ways and 9 slower ways for 4 cores). One more thing to add to the list of stuff to experiment with!
  • 5j3rul3 - Monday, October 4, 2021 - link

    Hope there's display efficiency measurements for iPhone 13 and iPhone 13 pro's display

    And, I'm so curious that why there's no 60 Hz VRR smartphones?
  • 5j3rul3 - Monday, October 4, 2021 - link

    The iPhone's VRR is interesting I think, and hope some detailed analysis on it.

Log in

Don't have an account? Sign up now