Blue Sky Creek: An Intel 4 + PowerVia Test Chip, Based on Crestmont E-Cores

To put PowerVia to the test and to prove that it’s working as expected, Intel’s validation vehicle for the technology is a chip they’re calling Blue Sky Creek.

Derived from Intel’s Meteor Lake platform, Blue Sky Creek uses two dies of E-cores that are based on Intel’s Crestmont CPU architecture. The reason Intel is using Crestmont here is two-fold: first, it was originally designed for Intel 4, making it a good candidate for porting over to the Intel 4 + PowerVia process. And second, because E-cores are tiny; the quad-core test dies are just 33.2mm2 (4mm x 8.3mm) in size, making them a good balance between complexity for testing and not having to actually yield a massive die on an experimental process node.

Intel isn’t focused too much on the performance of the E-cores in Blue Sky Creek. But they do note that the designed frequency was 3GHz at 1.1v.

With regards to the bigger picture, Big Sky Creek’s existence is part of Intel’s grand plan to mitigate the risk of introducing two major technological changes within the same process node – a problem that hit Intel rather hard with the overly-ambitious development plan for their 10nm (Intel 7) process node.

As outlined by the company back in 2022, of the two technologies, PowerVia was considered the riskier of the two. For that reason, Intel would be developing an interim test node just for PowerVia, allowing them to work on the technology separately from RibbonFETs. Ultimately, if PowerVia development had not progressed as expected, Intel could still do RibbonFET development, and bring out chips sans-PowerVia.

For similar reasons, you won’t find much discussion of RibbonFET from Intel for the VLSI conference. While it’s an important technology for the company, it’s essentially a sure-thing for Intel. The company won’t even be the first fab with GAAFET technology, so while RibbonFET does come with its own challenges, intel didn’t need to prepare any risk mitigation strategies for it in the same way as they did PowerVia.

PowerVia In Practice: Intel’s Finds 30% Reduction in IR Droop, 6% Higher Clockspeeds, Ready for HVM

Diving into the results of Intel’s PowerVia papers, the company has broken out their results for Blue Sky Creek on a metric-by-metric basis, looking at everything from chip density to performance to thermals.

Starting with chip density, here’s a look at the size of the high performance (HP) library cells that Intel developed and fabbed for their test chip, and how those cells compare to the equivalent Intel 4 cells. As noted earlier, the shift to PowerVia has allowed Intel to relax the pitch of the critical M0 metal layer, enlarging it from 30 nm to 36 nm. The other major parameters of the node, such as the fin pitch and contacted poly pitch (CPP) remain at 30 nm and 50 nm respectively.

Yet, those changes, combined with Intel’s ability to reduce the number of fins in use from 3 to 2, result in an overall smaller cell. Thanks to PowerVia, Intel was able to bring the library height down to 210 nm, from 240 nm on Intel 4. And with the CPP holding constant at 50 nm, that means the overall cell size has been reduced by 12.5%, despite not using a formally “denser” node.

Meanwhile, this disclosure also gives us a proper look at the total number of layers involved in the two chips. Whereas a standard Intel 4 chip will have 15 layers plus the redistribution layer (RDL) all on one side, the PowerVia test chip had 14 layers on the signal (front) side, and another 4 layers plus the RDL on the power (back) side. That is a net gain of 3 layers overall, so at least as far as Intel’s test chip goes, it’s more complex in terms of the total number of layers used. But on the flip side, all of those new layers come on the power side of the chip, where they’re all relatively large and easy to fab. Which is why Intel considers the additional layers a minimal drawback compared to not having to manufacture a 30 nm pitch M0 layer.

The density of these cells is also quite impressive. By moving to backside power delivery, Intel was able to utilize 95% of the space within one of the denser spots within the E-core cell. Unfortunately, Intel didn’t give comparable numbers for E-cores on Intel 4, but in general, the utilization is not quite that high.

As for the electrical performance of the E-cores, as expected, PowerVia delivers a significant reduction in IR Doop. Intel measured a 30% reduction in droop on their test chip as compared to an Intel 4-built E-core, and an even greater 80% (5x) reduction in droop at the actual chip bump level.

That clean power delivery, in turn, improves the compute performance and the energy efficiency of the chip. Besides the direct efficiency gains from losing less energy to resistance, constructing an E-core with PowerVia technology improved the maximum frequency (fMax) of the core by 6%. Intel doesn’t offer a more detailed explanation as to why this improved their clockspeeds, but I suspect it has to do with a higher voltage actually reaching the transistors themselves, allowing them to clock a bit higher.

And while a 6% clockspeed uplift isn’t a massive gain, it’s essentially a “free” improvement coming from a technology that is designed to improve the manufacturability of a chip. Intel has worked harder to get smaller clockspeed improvements in the past.

Interestingly, Intel did find that the new IR Droop values were not the same across all of the E-cores. Whereas the standard Intel 4 chip had a fairly consistent droop over all 4 cores, the droop for the test chip was between 60 mV and 80 mV, depending on the core. As this is a research presentation, Intel doesn’t go into the product ramifications of that, but assuming that production chips have a similarly wide range of variability, it may mean we see a greater emphasis on favored/prime cores in future products.

So PowerVia/BS-PDN works. But can Intel manufacture it at scale? The answer to that is also yes.

Accord to Intel, the defect density for their experimental Intel 4 + PowerVia process node is only about two quarters behind the Intel 4 process itself (which is already in HVM). Meaning that not only is the defect density low enough to be suitable for mass production in short order, but if Intel were scaling this specific node up for production, they would have similar chip yields as current, non-PowerVia Intel 4 chips in just two quarters.

Similarly, Intel reports that transistors built on the PowerVia process are very similar to those of the Intel 4 process. Which in this case, is very much a good thing, as it means those transistors aren’t doing unexpected things that impact performance or chip reliability. For that matter, Intel also noted that they observed no power-related reliability violations on the test chip, demonstrating that despite the significant changes to power delivery, the introduction of backside power delivery did not result in a less reliable power delivery system for the chip.

And while Intel isn’t going into the exact measures they’re employing to mitigate the thermal impacts of the transistor layer no longer being at the top of a flipped chip, the company is publishing data showing that the mitigations they have undertaken have been successful.

When plotted against the thermal response curve for an Intel 4 chip, Intel’s test chip demonstrated a very similar thermal response curve. Which is to say that at a given power level, the resulting temperatures were in-line with an Intel 4 chip. And as you may notice from Intel’s chart, they even went ahead and overfed the chip a bit to simulate even higher thermal loads, to better characterize the thermal response curve and to make sure thermal scaling wasn’t breaking down at higher thermal densities.

As noted earlier, thermals/cooling are one of the two big product-level challenges with backside power delivery. Placing transistors in what’s become the middle of the chip has not done chip cooling any favors, but Intel believes they have developed the necessary mitigation strategies to bring PowerVia chips in line with traditional frontside-fabbed flip chips.

Those mitigations go for debugging, as well, which was the other challenge with BS-PDN. Intel has developed a suite of new and modified debugging techniques to deal with the fact that both sides of a chip are now in use. And while, to quote the abstract of Intel’s paper “Failure debug and defect isolation is complex due to the presence of metallization on both sides of the wafer,” ultimately, Intel was able to develop the necessary tools.

Interestingly, Intel even placed some “Easter Egg” defects within the chip’s design in order to provide some semi-controlled defects for Intel’s validation teams to work against. According to Intel their validation teams found all of those eggs with their PowerVia debugging tools, helping to prove the validity of those debug processes.

PowerVia To Land in Intel Chips in 2024

Wrapping things up, ahead of next week’s VLSI conference Intel is laying out a very convincing case that they are on the right track with their PowerVia backside power delivery technology development. Having a complex test chip up and running is a big deal in this regard, as having actual data and experience to draw from is a major step towards fine-tuning the technology for high volume manufacturing, all the while showcasing that Intel is so far meeting their aggressive fab development goals.

Ultimately, PowerVia is perhaps the single biggest make-or-break moment for Intel in terms of fully recovering momentum and potentially retaking leadership within the silicon lithography business. If Intel can deliver on its promises, the company is expecting to be at least two years ahead of TSMC and Samsung in deploying backside power delivery – and that means at least two years of reaping the cost and performance benefits of the technology. TSMC for its part is not expecting to deploy backside power until its N2P node in late 2026 or early 2027, while it remains unclear when Samsung will make their own transition.

As for Intel, if everything continues to go to plan, Intel will begin high volume manufacturing with PowerVia in 2024, when the company is scheduled to bring both its Intel 20A and Intel 18A processes online. The first consumer processor to launch using the technology will be Intel’s Arrow Lake architecture, which will be a future generation Core product built on the 20A node.

Backside Power Delivery: The Story Thus Far
Comments Locked


View All Comments

  • brakdoo - Monday, June 5, 2023 - link

    Thermals are a mess. 30% of core area for thermal stuff? What's the benefit of backside power then (just 6% frequency?)? How is their "normalized" power and temperature compared to the regular Intel 4 chip? What was the size of the non backside Intel 4 chip?

    At >> 10mm2 for 4 E-Core these E-cores are much bigger than regular E-Cores on Meteor Lake (we've seen die shot leaks)

    Zero information... Please be more critical and ask these questions when you have the opportunity to directly talk to them instead of just posting their stuff.

    BTW: They should've used P-cores instead of E-cores when it comes to thermals.
  • jjjag - Monday, June 5, 2023 - link

    Like anybody from AT will attend VLSI Symposium and be able to ask meaningful questions...

    VLSI Symposium is focusing on backside power/PowerVia this year, as every major foundry is offering it at the 2nm node (along with ribbon/GAA FET and some other advanced packaging techniques). Intel is going to present some details on their implementation. The focus is the improvement of power via alone, not how big the e-cores are compared to meteor lake.

    You are missing the point of the article, the paper, and the content of VLSI Symposium this year. Go look at the program, then once the conference is done in a couple weeks go read the papers.
  • Ryan Smith - Monday, June 5, 2023 - link

    To be sure, we did have a chance to ask questions last week. But those ended up mostly centered around likes like the carrier wafer and wafer slimming, the E-cores, the defect rate, and EDA tools. There are always more questions than there is time to get them answered, at least initially.
  • vlsi_dude - Sunday, July 23, 2023 - link

    The 30% of core area for thermals was to to insert redundant thermal monitors (+ trying several thermal monitoring techniques to find which performs better) and also to try out several special thermal mitigation techniques. One can only afford to do this on a test chip and the learnings will be incorporated in the products. The comment about 30% was to convey the point that the design team took the thermal seriously and spent "much area" on getting high quality and irrefutable thermal data and to also study the thermal sensitivities
  • III-V - Monday, June 5, 2023 - link

    Wow, 6% higher clock speeds is pretty nice in this day and age. Wonder what the Intel 4 process delivers vs Intel 7 (if anything at all)
  • TristanSDX - Monday, June 5, 2023 - link

    For users
    + 6% higher clock, 12% higher density
    - harder to cool, may throttle decresaing clocks gain
    For Intel
    + lower cost for M0
    - complex debug (higher cost for next gen cores design), more layers (additional cost despite easy to make), more silicon for carrier, additional costs for thinning and other processing

    Overall not so beneficial, TSMC and Sansung have right not to rush with it until it is really needed.
  • thestryker - Monday, June 5, 2023 - link

    The article states that Intel worked around the thermal issue with their design so harder to cool not so much. The shift in pitch is mostly about offsetting the additional costs so this also isn't so much a thing. If the pitch shift alone allows for them to drop one layer of multipatterning it has more than paid for itself.
  • my_wing - Tuesday, June 6, 2023 - link

    Lower cost for M0, that is a big plus, this is where you needed EUV (Multiple patterning), the article is actually suggest is M1 layer having benefit.

    Harder to cool? I think the backside power is mainly copper wires, and copper conduct heat well, look at your heat sink. Yes it can make it worst but I think the situation is not as bad as you guess.

    complex debug? More Layers ??? negative for Intel not necessary, even if there are more layers if each layer become simpler then is actually easier to debug. You have power and signal cable tango each other. The layer is more simple.

    TSMC and Samsung can say wherever they like but it can meant that TSMC and Samsung underestimate the technology.
  • ikjadoon - Monday, June 5, 2023 - link

    If Intel can deliver on its promises, the company is expecting to be at least two years ahead of TSMC and Samsung in deploying backside power delivery – and that means at least two years of reaping the cost and performance benefits of the technology.


    But that's only ahead of Intel's own nodes, whose performance isn't being detailed quite yet. Intel should pit their Intel 4 / Intel 3 / Intel PDN libraries onto an industry-standard core and even compare it to data for those same industry-standard cores at other fabs.

    That's how you'd sell IDM 2.0 to investors & tech media (the only people that don't know this data already, but hold significant power over Intel's future).
  • trivik12 - Monday, June 5, 2023 - link

    Why dont Intel make intel 3 with Power Via. That should help GNR and SRF significantly.

Log in

Don't have an account? Sign up now