Pentium 4 3.46 Extreme Edition and 925XE: 1066MHz FSB Support is Here

Does the 1066MHz FSB Improve Memory Performance?

Quite possibly the biggest feature of the 1066MHz FSB today is the fact that it runs at a clock multiple of DDR2-533's frequency. Why is that such a big feature? It's analogy time:

If two people are having a conversation and they can both talk and listen at the same rate, then the conversation will flow as smoothly as possible. If person A talks and listens slower than person B, then person B will always be waiting for person A instead of communicating as fast as possible - a frustrating situation for those that have been here before. Running a FSB and memory bus asynchronously is just as frustrating to the CPU; if the two frequencies aren't synchronous then there is an additional latency penalty incurred while transferring data between the two buses and because of that additional latency penalty, there is a reduction in usable bandwidth.

With the original 925X chipset we were a bit unhappy to see that the Pentium 4's 800MHz FSB was paired with DDR2-533, creating one of those frustrating asynchronous situations. But with a 1066MHz FSB (266MHz x 4), the 925XE can communicate synchronously with DDR2-533 (266MHz x 2), thus reducing memory latency and increasing memory bandwidth in theory. What do we see in practice? To answer this question we look to two trusted measures of memory bandwidth and latency: CacheMem and ScienceMark 2.0.

First looking at latency we see that with the 1066MHz FSB, memory latency with DDR2-533 looks like it's hardly improved. Running the FSB at 1066MHz manages to shave off a just a few clock cycles.

We look at ScienceMark and see the same basic situation but with slightly improved performance; looking at the absolute latency values in nanoseconds we see that the 1066MHz FSB manages to reduce memory latency by around 2 - 6%.

The reduction in latency isn't insignificant under ScienceMark, but what about its affects on memory bandwidth?

Looking at Cachemem once again we see an increase in memory bandwidth of just under 4%.

ScienceMark appears more considerate of Intel's hard work and shows a 9% increase in memory bandwidth. The thing to keep in mind here is that the improvement in memory bandwidth will depend on the types of applications run, but the ScienceMark and Cachemem results should give you an indication of the range of improvements to be expected in applications that are memory bandwidth limited. In those applications that aren't currently bound by memory bandwidth, the impact will be much less.

What is important to keep in mind here is that DDR2 is still running at relatively high latencies. Even while running synchronously with the FSB, the 925XE and DDR2 combination still posts higher memory access latencies than 875/DDR400 platforms thanks to DDR2's high memory timings. We were able to run 3-3-3-12 timings on our DDR2 test platform by keeping memory voltage at a safe, but overclocked, 2.0V, but anything faster than that was too much for today's DDR2-533. It will take even lower latency DDR2 in order for even the 925XE platform to show some further performance advantages.

Given the relatively small increases in memory bandwidth and decreases in latency, the extra 66MHz of the 3.46EE will have to go a long way in order to gain any more ground for Intel. Let's see how things shape up in some real world tests.