Multiple Front Side Buses; Coming to an Intel Server Near You
by Kristopher Kubicki on November 4, 2004 4:13 AM EST- Posted in
- CPUs
Next Generation Processors
Unfortunately, next generation processor architecture seems
more amok than anything we could have imagined (to be fair, this goes for AMD too, but that is a different article). There are rumors of a next
generation NetBurst processor, dubbed Cedarmill (or Cedar Mill), floating
around. Sources tell us that Cedarmill looks like Iriwindale/Prescott 2M on
the 1066FSB, although the Intel roadmaps indicate absolutely nothing about it.
We have also heard rumors that it could be a 90nm part shipping in very late
2005, or perhaps a 65nm part shipping in 2006. However, the roadmaps make zero
mention of this chip, so take those rumors with a grain of salt for now.
Intel has dual core SKUs slated for every facet of its
processor technology, even if just as a code name. Before dual core we expect
to see the launch of Iriwindale (Prescott 2M) - which does not seem to be much
other than Xeons with 2MB L2 cache, DDR2 and EM64T - and no plans to go to
4GHz. By the time 2006 rolls along, Intel has three server CPU code names on the table:
Dempsey (Iriwindale Successor), Paxville (Cranford successor) and Tulsa (Potomac successor).
Dempsey looks like the DP/UP solution while Paxville and Tulsa are the MP solutions.
Iriwindale, if you don't know already, is the upcoming Prescott successor. We shouldn't really
call it a successor, as Iriwindale is identical to
Nocona with 2MB of L2 cache (90nm, 800MHz FSB). However, the core does get a
little freshening with EM64T integration and Enhanced Speed Step instructions.
Expect to see Iriwindale/Prescott 2M in Q1 next year, with speeds starting at
3GHz and ramping to 3.8GHz.
After the dust settles when Iriwindale replaces Nocona,
Intel has the roadmaps for Dempsey, Tulsa and Paxville laid out. "Tulsa" and "Paxville" are
fairly self explanatory; Tulsa is the Cranford/Potomac
replacement, and Paxville is the eventual Tulsa successor. There are footnotes
indicating a ramp up of dual core technology for the multiprocessor (MP)
market, and the dual FSB Twin Castle chipset would also designate that sort of migration.
Footnotes on the roadmap indicate both Paxville is definitely a dual core
processor, although we suspect its successor Tulsa would be dual core as well.
Tulsa is the only 65nm processor mentioned on the roadmap, although we also
expect Yonah (next generation Pentium M) to utilize 65nm.
Dempsey, the Iriwindale replacement, is certainly dual core
(according to our roadmap). Dempsey is slated for H1'06, somewhere just after
the rumored Cedarmill launch.
Below you can see a list of processors and some details.
- Prescott 2M: Identical to today's Prescott with some additional features like 2MB L2 cache. Still 800MHz FSB, 90nm process. New features include EM64T and Enhanced Speed Step. Slated for Q1'05.
- Iriwindale: Prescott 2M for UP and DP servers/workstation. Slated for Q1'05.
- Smithfield: Dual core Desktop processor. 800MHz FSB, EM64T, Enhanced Speed Step, XD and 1MB L2 cache per core. Produced on the 90nm process. Slated for Q3'05.
- Dempsey: Dual Core Iriwindale replacement, nearly identical to Smithfield. Slated for H2'05.
- Cranford: Xeon MP CPU with 667MHz FSB, 1MB L2 cache. Also supports XD, EM64T. Expected Q1'05.
- Potomac: Xeon MP CPU with 667MHz FSB with 1MB L2 and up to 8MB L3 cache. Expected for Q2'05.
- Paxville: Successor to Potomac/Cranford. Expected H1'06.
- Tulsa: Successor to Paxville. Expected H2'06.
- Alviso: 90nm successor to Dothan (Pentium M). Expected to launch Q1'05.
- Yonah/Jonah: 65nm, dual core successor to Alviso for the Napa platform. Expected to launch Q1'06.
- Cedarmill: Iriwindale/Prescott 2M but with a 1066MHz FSB. Rumored for late '05 or early '06.
Some of the technologies abbreviated are also listed below. The technologies labeled enterprise are mostly geared toward Itanium processors.
- EIST: Enhanced Intel Speed Step Technology; modifies the frequency on the fly to keep thermal and power consumption down.
- Foxton Technlogy (FT): Modifies CPU frequency on the fly, sort of like EIST (enterprise)
- DBS: Demand Based Switching; EIST for IA64 during idle time (enterprise)
- Pellston Technology (PT): Higher system RAS via cache redundancy (enterprise)
- Silvervale Technology (ST): Hardware virtualization (enterprise)
- Vanderpool Technology (VT): Hardware virtualization
- AMT: Active Management Technology; Out of Band system management independent of operating system.
- LaGrande Technology (LT): Hardware based security measures against software security flaws.
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Peter - Monday, November 29, 2004 - link
Independent CPU busses on the north bridge?*yawns* This is hardly news.
Pentium III Serverworks "Champion HE" chipset let you combine twin north bridges so you'd end up with two CPU busses (and two RAM controllers, incidentally).
AMD Athlon MP architecture had twin CPU busses out of one (AMD 762) north bridge chip.
AMD 64 has taken the next step beyond that already, eliminating CPU FSB altogether by planting the RAM controller into the CPU.
IntelUser2000 - Saturday, November 27, 2004 - link
Well sorry your theory is crap. Only reason Prescott is slower than Northwood(slow being 2-3% average, which is insignificant) is because Prescott has higher L1 and L2 latency, otherwise Prescott would have been faster.Ibrahimmhmd - Tuesday, November 16, 2004 - link
The only reason Intel is exhausting their existing technologies is due to the Tejas screw up. If you still remember, Tejas is the pre-Cedarmill processor which was supposed to take over the ailing Prescott. Prescott had speed paths problems even at 2.0Ghz initially. So Intel knew hitting 4.0Ghz will remain a dream for quite some time. With Tejas cancelled in favour of the Centrino cores for the future, Intel had to start switching over to some marketing tricks to make sure we forget about the GHz rules "knowledge" Intel has, for as long as they have existed, instilled in all its users. Yes, that's when they came up with the model number crap. Think about it. It paves way for Intel's introduction of the dual-core processors apart from the higher IPC centrino cores - how do you tell 6-pack-joe a 5GHz part will perform SLOWER than a 3GHz part? Coz it's got dual-core? What's a core to Joe?Anyway, back to the main topic. Since Prescott is practically slower than Northwood clock-to-clock cache-size-to-cache-size, Intel took the decision to market Prescott with a larger cache. Even with that, there're quite a lot of apps that suffered from the longer pipeline Prescott had (due to the attempt to bump up the frequency, as well as some thing else ;-P ). At that juncture, Intel knew they were in deepest shit they have ever been since the Pentium FP flaw. They knew they were definitely losing the performance crown to AMD. To try to keep up with them and show us that they're still a competent rival to AMD, they had to dig out their dusty designs, tweak them and sell as new products until their next generation processors comes out.
In the meantime, they'll continue selling their CPUs as if they're still diligently churning out new technologies. You believed the latest Intel processor you bought is using the latest technology don't you? Don't you just love marketing.
Anyway, that's just my theory. Feel free to comment.
ceefka - Monday, November 8, 2004 - link
#13 This dedicated (non on-die) memory controller sounds like a system that is going to suffer from latencies between the components. There are too many. Isn't this also an expensive approach? Designing a mobo for this concept will not easy, will it?If Intel still relies on big caches and doubles their FSB (DIB) I think they're exhausting one old technology after the other, while adopting less fortunate ones like DDR2. I still think/hope they've something big up their sleeve, but this is not it.
While Intel can top AMD on various benchmarks, it takes costly technology that seems to be at the very end of its potential. I'd still favour an AMD 939 CPU because of the potential.
sprockkets - Sunday, November 7, 2004 - link
Hmmm... perhaps a memory controller and then a PCI express controller, then a sb with all the usual stuff?IntelUser2000 - Saturday, November 6, 2004 - link
"1066 FSB might actually help more if it were paired with a 1 MB cache chip, but we'll have to wait a while to see that."I think that's not the reason 1066FSB gives no performance increases in EE performance. I think it has to do with the fact that DDR2-533 has more than 33% higher latency than DDR-400 so in order to completely fill 1066FSB requirements you need higher than DDR2-533, preferrably DDR2-667. Do you see that DDR2-400 was slower than DDR2-533? Why is it slower when in dual-channel mode it perfectly matches 800MHz bus? Its because of latency. 800MHz bus needs DDR2-533 and 1066MHz bus needs DDR2-667.
JarredWalton - Saturday, November 6, 2004 - link
#12 - The dedicated memory controller will become a separate chip from the Northbridge and Southbridge. We will end up with three chips. This decouples the RAM support from the NB, and since the NB has become quite complex, that makes it even easier for Intel to adopt a new type of RAM if it sees an advantage in doing so. I believe that it will also allow somewhat faster latencies, but only real product will actually let us know that for sure.As far as the "independent" part and dual-channel vs. DIB (Dual Independent Buses), dual-channel is similar in that it's a wider, faster memory bus. I'm not sure whether the memory controller can actually send different requests out concurrently on each channel, however, and that is definitely something that DIB should provide. HyperTransport is a different approach to the same problem, but we'll see how "different" it really ends up being.
Right now, must of what we know about DIB comes from the Intel roadmaps, which are full of marketing information and short on technical detail. What we do know from the past is that with its deeper buffers and quad pumped FSB, NetBurst has always been more appreciative of memory bandwidth. 1066 FSB might actually help more if it were paired with a 1 MB cache chip, but we'll have to wait a while to see that. For dual-core (or multi-core) processors, however, it is definitely helpful for Intel. The same can be said of Xeons: DIB will give each socket much better RAM support, so Intel might see scaling similar to what Opteron is getting. I'm sure that's what they're hoping for, anyway.
sprockkets - Saturday, November 6, 2004 - link
And the best part is 1066FSB has no effect on performance whatsoever.I'm not sure though what you mean by "dedicated memory controller." Don't all usual chipsets have a dedicated memory controller? And if you are saying too that Twin Castle has dual memory controllers, don't all current dual channel chipsets have 2 memory controllers already on it? Or does this mean that there will be 2 dual channel memory controllers on the NB? DOes this mean that each core then gets its own memory bank?
Even weirder, you say that there will be two buses per a socket, namely, for a dual core socket. Does that mean that each core gets a FSB? Wouldn't be more logical like AMD to have a 2ghz bus for both cores? Does this mean that Intel's 2 cores can't even talk to each other?
If you say so Intel...
Reflex - Friday, November 5, 2004 - link
#9: You can prefer it all you want, but Intel has hit some fundamental laws of physics that won't go away. Expect larger cache's, higher FSB's, and multiple cores for the forseeable future...Which is good, it would be nice to see features rather than Mhz to increase performance in my opinion.PorBleemo - Friday, November 5, 2004 - link
This is basically giving Intel processors what the AMD processors had all along:1. Independent Hypertransport Buses
2. 64-Bit Integer Processing
3. Real-Time Clock Throttling
We'll just have to see if the heat emissions will still be twice as high as the AMDs though. :)