Having dropped out of the race for leading-edge manufacturing technologies in order to focus on specialty fabrication processes, GlobalFoundries has pinned some big hopes in manufacturing RF-SOI chips for various 5G applications, as well as FD-SOI chips for low-power devices. This week the company signed a memorandum of understanding (MOU) with GlobalWafers Co. (GWC) to develop a long-term supply contract for 300 mm SOI wafers, GloFo's second long-term SOI wafers supply agreement (WSA) in less than a year.

Once primarily used to build leading-edge processors, silicon-on-insulator (SOI) technology is used today for a wide variety of applications, including those that need an ultra-low power consumption (SoCs and MCUs for IoT applications), high voltages (analog/mixed signal), or high resistivity (4G and 5G front-end modules [FEMs] for smartphones). All of these are made using so-called specialty manufacturing technologies, and to that end they are of tremendous interest for GlobalFoundries. Meanwhile, considering the rise of 5G and IoT, RF-SOI and FD-SOI are the most promising technologies when it comes to producing the necessary chips in high volumes.

Nowadays, GlobalFoundries operates seven fabs: four 300-mm fabs (including the Fab 10 in East Fishkill, New York) and three 200-mm fabs. The company’s largest 300-mm Fab, Fab 1, is used exclusively to make SOI products, Fab 7 in Singapore uses both bulk and SOI technologies, and Fab 10 can also process wafers using SOI-based processes. In addition, GlobalFoundries is building another 300-mm fab in Chengdu, China, which will also be used to make chips using its 22FDX technology. Finally, the foundry’s 200-mm facilities can all use SOI wafers as well.

Being the largest consumer of SOI wafers in the world, GlobalFoundries sources 200-mm and 300-mm substrates from both Soitec, the world’s largest producer of SOI wafers, as well as GlobalWafers Co. In fact, in just the last year GloFo and Soitec signed a multi-year 300-mm SOI wafer supply agreement, which builds upon a WSA signed in 2017. As it turns out, GlobalFoundries needs even more 300-mm SOI wafers for its advanced RF SOI technologies, so the company is going as far as agreeing to help GWC ‘significantly expand’ its SOI wafer manufacturing capacity as part of the new contract.

GlobalFoundries, Soitec, and GlobalWafers Co. naturally do not disclose how many wafers are consumed by the chip maker. Regardless, it looks like we are talking about a significant expansion of SOI usage at GlobalFoundries.

Bami Bastani, senior vice president for mobile and wireless infrastructure at GlobalFoundries:

“Mobile, wireless, and 5G represent a significant opportunity for GlobalFoundries, and our vital RF technology is featured in more than 85% of smartphones on the market today. We are pleased to collaborate with GlobalWafers, and look forward to working with them to develop and qualify an additional supply of 300mm SOI wafers to integrate into our manufacturing processes and help meet the growing demand for our RF SOI solutions.”

Tom Weber, senior vice president and chief procurement officer at GlobalFoundries said the following:

“Given our market position, it is in our best interest – and the best interest of our clients – to build out and diversify the supply chain for 300mm SOI wafers. GlobalWafers is the right partner for us to make this happen.”

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Source: GlobalFoundries

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  • ksec - Friday, February 28, 2020 - link

    Except it really isn't "acronym". In Tech you dont define everything up front like FDD, TDD, CDMA, SQL, DRAM, CPU, M-MIMO, FPGA, GAA, FinFET, etc.. Depending on your reader's understanding, unless they are very rare and not used much, you are expected to know them. And in the case Anandtech is one of the rare site that focuses on the relatively higher end. SOI isn't something brand new, and if you dont know, you are expected to look it up. No one will spell out Dynamic Random Access Memory in PC publishing or Massive Multi-input Multi-output Antenna in 4G / 5G publishing.
  • prisonerX - Friday, February 28, 2020 - link

    YSAK, right?
  • Dizoja86 - Friday, February 28, 2020 - link

    Yeah, you don't use an abbreviation multiple times before you give the definition. Anyone who has written a 12th grade essay knows that much. I also highly doubt that the majority of readers on this site know that particular abbreviation off the top of their heads.
  • Holliday75 - Friday, February 28, 2020 - link

    I am guilty. I have seen it used over the years, but could not remember.
  • Kevin G - Thursday, February 27, 2020 - link

    I wonder if this is a move to secure wafers long term if the fabs who are currently on leading edge processes do end up adopting SOI down the road. Much of the technology currently in use on bulk leading edge can be made to work with SOI though it is currently not adopted due to an imbalance in cost/benefit. As transistors continue to get smaller that could change.
  • FunBunny2 - Thursday, February 27, 2020 - link

    so sad... still no 450mm wafers. progress is so slow.
  • Santoval - Friday, February 28, 2020 - link

    450 mm wafer plans have been canned, due to their dubious ROI (either the same or less than that of 300 mm wafers) and the much higher difficulty and cost of handling and processing them. While with 450 mm wafers you can have many more dies per wafer, if the wafers cost 4 times more than 300 mm wafers (as is currently estimated) the high numbers of dies per wafer does not really matter.
  • Zizy - Friday, February 28, 2020 - link

    Nobody cares about 450mm. There is a very small improvement in utilization of wafer until you get to very large dies, and those aren't really viable due to yield.
    Additionally, you get troubles in every single step on the way - people making ingots have it harder, all tools need to be redesigned and made bigger, and people carrying those hot lots around also complain because of twice the weight.
  • Santoval - Friday, February 28, 2020 - link

    Silicon ingots for 450 mm wafers are not just twice as heavy as those for 300 mm wafers. They are *three* times heavier, at roughly one ton each. Furthermore, a FOUP (a special plastic enclosure for holding and carrying wafers) with 25 450 mm wafers weighs a whopping 45 kg, while a FOUP with 25 300 mm wafers weighs only 7.5 kg. Everything (from ingots to step-and-scan systems) needs to be bigger, much heavier, quite costlier and more time consuming to make the transition to 450 mm wafers a reality.
  • dotjaz - Friday, February 28, 2020 - link

    Why would you need 450mm wafers? What progress does it represent beyond one number?

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