ASUS P5E3 Deluxe Overclocking: DDR3 Takes Front Stage
by Kris Boughton on November 20, 2007 4:00 AM EST- Posted in
- CPUs
BIOS Setup and Tweaking, Continued
DRAM Static Read Control: Auto, Enabled, and Disabled. We were unable to affect any measurable performance change because of toggling this setting. This setting is curious by its very nature as Ai Transaction Booster (explained below) manipulates the MCH Static Read Control Delay setting directly, implying there would be no reason for this option.
DRAM Dynamic Write Control: Auto, Enabled, and Disabled. See above.
Ai Clock Twister: Auto, Light, Moderate, and Strong. This setting controls the number of memory access phases that are "pulled-in" to the next lower (higher performance) Static Read Delay value. In essence, this allows for smaller, incremental performance gains if the user is unable to achieve stability when using the next lower Static Read Delay value.
Ai Clock Skew for Channel A/B: This setting allows you to either advance or delay the signal timings for Channel A or Channel B DIMMs. Because it's not possible to locate all memory modules an equal distance from the MCH, it's important to be able to adjust signal timing to ensure all data (or requests for data) arrive at the same point at precisely the same time. When experimenting with this setting either slightly delay Channel A (since it's closer to the MCH) or advance Channel B - do not change both simultaneously unless you find you need more than 350ps (picoseconds) of total skew (highly unlikely).
Ai Transaction Booster: Auto, Enabled (Boost: 1-8), and Disabled (Relax: 1-8). This is probably one of the most important BIOS settings when it comes to extracting every possible bit of performance from the system. Setting these fields can improve total memory bandwidth up to 15% and produce a considerable reduction in access latency.
Static Read Control Delay, sometimes referred to as Performance Level, is a primary MCH "timing" value and has a rather significant impact on memory read performance as well as overall memory access latency. In case you are wondering why low access latency matters, we submit to you the following quick-and-dirty response: improved memory latency (courtesy of the Integrated Memory Controller/IMC) is the primary reason that AMD Athlon 64 chips have performed so well. Latency is one of the few areas where AMD maintains a lead over Intel, and Intel will move to an IMC design late next year (starting with Nehalem).
Much like primary memory timings, this MCH "timing" is measured in clock cycles and is relative to the base transmission frequency (2 x FSB). This explains why Static Read Control Delay should increase as FSB rates rise. Similar to memory timings, maintaining a lower value longer with the proper application of MCH voltage can lead to improved performance. In other words, "boosting" the Ai Transaction level may require a higher MCH voltage than would be otherwise required if a more relaxed level were set.
Because these settings effectively apply an offset to the default value it can sometimes be difficult to confirm exactly what is going on - it is almost like flying blind. Thankfully, a wonderful tool exists that reads and reports "Performance Level" from within Windows, allowing us to verify that the board is operating as intended. Memset 3.4 (beta 3), available as freeware, can be found through a simple search using your favorite search engine. Here we see Performance Level, as reported by Memset 3.4, as well as Command Rate and memory latency from EVEREST 4.20.
Auto allows the BIOS to set the values automatically which, through simple experimentation and observation, has been simplified to the following relationship: Static Read Control Delay (default) = tCL. Knowing this makes adjusting the value rather simple. Keep in mind that workable values are in the range of 1-3 (boost or relax) only; selecting values from 4 through 8 will always result in a POST failure.
For example, with memory set to DDR-1600 6-6-6-15, the BIOS will establish a default Static Read Control Delay of 6. Setting Ai Transaction Booster to Enabled with a Boost Level of 1 results in a final Static Read Control Delay setting of 6 - 1 = 5. Alternatively, selecting Disabled with a Relax Level of 1 results in a final value of 6 + 1 = 7. Just like in the case of memory timings, lower is tighter (higher performance).
Finally, a simple rule to keep in mind when setting Static Read Control Delay - 4 requires a CAS Latency (tCL) of 6 or lower, 5 requires a tCL of 7 or lower, and 6 requires a tCL of 8 or lower. There are no other known limitations at this time.
CPU Voltage: Maximum of 1.7000V. Our experience with the ASUS P5E3 Deluxe has shown a rather large voltage offset when it comes to VCore. For example, setting 1.4675V in the BIOS results in an in-Windows idle voltage of ~1.4250V by DMM. Under load we see the voltage settle out as low as 1.39V. While we understand the need and requirement for VDroop, a total difference in programmed BIOS voltage to full-load voltage of more than 0.07V is excessive. Keep this in mind when setting this value if you already know the minimum voltage your CPU needs for stable operation or utilize the load-line calibration setting listed below to reduce VDroop.
CPU PLL Voltage: Maximum of 2.78V. Out of all the voltages the user can manipulate this one is by far the most dangerous. Maximum vCPUpll, as established by Intel, is 1.60V (default for this board) making 2.78V a whopping ~75% over specification! (As an aside, this would be the equivalent of subjecting your 65nm CPU to a core voltage of over 2.5V). Exercise extreme caution when utilizing higher values as setting this value too high can result in the CPUs "losing cores" after being subjected to voltage in excess of ~2.0V. The good news is that we did not see an increase in overclocking potential with voltages above 1.68V.
DRAM Static Read Control: Auto, Enabled, and Disabled. We were unable to affect any measurable performance change because of toggling this setting. This setting is curious by its very nature as Ai Transaction Booster (explained below) manipulates the MCH Static Read Control Delay setting directly, implying there would be no reason for this option.
DRAM Dynamic Write Control: Auto, Enabled, and Disabled. See above.
Ai Clock Twister: Auto, Light, Moderate, and Strong. This setting controls the number of memory access phases that are "pulled-in" to the next lower (higher performance) Static Read Delay value. In essence, this allows for smaller, incremental performance gains if the user is unable to achieve stability when using the next lower Static Read Delay value.
Ai Clock Skew for Channel A/B: This setting allows you to either advance or delay the signal timings for Channel A or Channel B DIMMs. Because it's not possible to locate all memory modules an equal distance from the MCH, it's important to be able to adjust signal timing to ensure all data (or requests for data) arrive at the same point at precisely the same time. When experimenting with this setting either slightly delay Channel A (since it's closer to the MCH) or advance Channel B - do not change both simultaneously unless you find you need more than 350ps (picoseconds) of total skew (highly unlikely).
Ai Transaction Booster: Auto, Enabled (Boost: 1-8), and Disabled (Relax: 1-8). This is probably one of the most important BIOS settings when it comes to extracting every possible bit of performance from the system. Setting these fields can improve total memory bandwidth up to 15% and produce a considerable reduction in access latency.
Static Read Control Delay, sometimes referred to as Performance Level, is a primary MCH "timing" value and has a rather significant impact on memory read performance as well as overall memory access latency. In case you are wondering why low access latency matters, we submit to you the following quick-and-dirty response: improved memory latency (courtesy of the Integrated Memory Controller/IMC) is the primary reason that AMD Athlon 64 chips have performed so well. Latency is one of the few areas where AMD maintains a lead over Intel, and Intel will move to an IMC design late next year (starting with Nehalem).
Much like primary memory timings, this MCH "timing" is measured in clock cycles and is relative to the base transmission frequency (2 x FSB). This explains why Static Read Control Delay should increase as FSB rates rise. Similar to memory timings, maintaining a lower value longer with the proper application of MCH voltage can lead to improved performance. In other words, "boosting" the Ai Transaction level may require a higher MCH voltage than would be otherwise required if a more relaxed level were set.
Because these settings effectively apply an offset to the default value it can sometimes be difficult to confirm exactly what is going on - it is almost like flying blind. Thankfully, a wonderful tool exists that reads and reports "Performance Level" from within Windows, allowing us to verify that the board is operating as intended. Memset 3.4 (beta 3), available as freeware, can be found through a simple search using your favorite search engine. Here we see Performance Level, as reported by Memset 3.4, as well as Command Rate and memory latency from EVEREST 4.20.
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Auto allows the BIOS to set the values automatically which, through simple experimentation and observation, has been simplified to the following relationship: Static Read Control Delay (default) = tCL. Knowing this makes adjusting the value rather simple. Keep in mind that workable values are in the range of 1-3 (boost or relax) only; selecting values from 4 through 8 will always result in a POST failure.
For example, with memory set to DDR-1600 6-6-6-15, the BIOS will establish a default Static Read Control Delay of 6. Setting Ai Transaction Booster to Enabled with a Boost Level of 1 results in a final Static Read Control Delay setting of 6 - 1 = 5. Alternatively, selecting Disabled with a Relax Level of 1 results in a final value of 6 + 1 = 7. Just like in the case of memory timings, lower is tighter (higher performance).
Finally, a simple rule to keep in mind when setting Static Read Control Delay - 4 requires a CAS Latency (tCL) of 6 or lower, 5 requires a tCL of 7 or lower, and 6 requires a tCL of 8 or lower. There are no other known limitations at this time.
CPU Voltage: Maximum of 1.7000V. Our experience with the ASUS P5E3 Deluxe has shown a rather large voltage offset when it comes to VCore. For example, setting 1.4675V in the BIOS results in an in-Windows idle voltage of ~1.4250V by DMM. Under load we see the voltage settle out as low as 1.39V. While we understand the need and requirement for VDroop, a total difference in programmed BIOS voltage to full-load voltage of more than 0.07V is excessive. Keep this in mind when setting this value if you already know the minimum voltage your CPU needs for stable operation or utilize the load-line calibration setting listed below to reduce VDroop.
CPU PLL Voltage: Maximum of 2.78V. Out of all the voltages the user can manipulate this one is by far the most dangerous. Maximum vCPUpll, as established by Intel, is 1.60V (default for this board) making 2.78V a whopping ~75% over specification! (As an aside, this would be the equivalent of subjecting your 65nm CPU to a core voltage of over 2.5V). Exercise extreme caution when utilizing higher values as setting this value too high can result in the CPUs "losing cores" after being subjected to voltage in excess of ~2.0V. The good news is that we did not see an increase in overclocking potential with voltages above 1.68V.
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frede86 - Tuesday, September 2, 2008 - link
hey folksnice guide u made there m8.
but ive tryed to use that setup u recomment.
but doenst work. how come? is it because i use a dou core E8500?
Cheers
frede86 - Tuesday, September 2, 2008 - link
Core 2 dou*cEvin Ki - Saturday, February 23, 2008 - link
after reading the information on the AI transaction booster, and the Memset program, i decided to brave up, and give it a go. Memset indicated that my performance level was a 7. as my ddr2 CAS was 4, i assumed that the bios was relaxing my system a little. i simply disabled the booster option in bios with a relax of zero. rebooted, and re-ran Memset. nothing had changed. still a 7. any settings other than disabled and zero, in bios, will not POST. Memset allowed me to change the performance level to 6, apply, and save the change. nothing has changed in bios as a result of that change.my question is, what am i doing wrong, as i would expect to have seen something different in Memset with changing the bios to disabled and in effect lessening the relax?
i apologize if i have somehow missed the whole point, and do not understand this memory tweaking concept.
thanks
jwigi - Thursday, February 14, 2008 - link
Hi I have a P5k Premium and the contact between the heatsinks and the board aren't very good, i was wondering what size of screw you used and also if you needed to put any springs on them, i'm thinking of doing the same 'mod' you've done in your article on my board...thanks
plextor10000 - Thursday, January 10, 2008 - link
I was already one day playing with the settings of the mainboard, first tried to boost the E6850 from default 3Ghz to 3.6 , but could not make it stable in benchmarksSwitched to the Q6600 - and followed the guide , decrease the voltage for the CPU to 1.375 , for safety .
After step by step, i increased from 2.4 without any issue to 3.6 , running stable with my patriot 1333 on 1600
Thank you for this guide. Can i use the same settings for the E6850 also , or do i modyfie some settings to blaze the clocks of it ??
Ryujin - Sunday, January 6, 2008 - link
I recently got this board, and after reading this article, I really want to follow the advice therein and remove the thermal pads underneath the heatpipes/heatsinks and replace them with thermal paste, and replace all the plastic push-pins with screws/nuts.I've yet to start fiddling with the board, as I am still waiting for the CPU to arrive. A few pieces of advice I was looking for to ease my mind though:
- Would I be mad using Arctic Silver thermal compound, considering conductivity issues? (I could get ceramique, which is non-conductive, but it'll take quite a while, through the channels I wish to use).
- What diameter / length screws do you recommend? I figure 10mm M3 screws with lock nuts should do the trick... If they're too long, I should be able to screw them in with the heads facing the MB-tray.
- I'm going with a liquid cooling solution for my CPU. The P5E3 Deluxe included two fans that can be placed atop the heatsinks surrounding the CPU-socket for just such an occasion. However, I suspect they're rather noisy (are they?). Also, the case I'm using is the Coolermaster Cosmos, which does have ample chassi fans, so I'm wondering it is really necessary (time will tell, but I was wondering if anyone has any opinions on the subject).
cheers
kmmatney - Tuesday, November 20, 2007 - link
OK, looking at the graphs, it just seems like all I'm seeing is the benchmarks getting better with higher overall cpu speed. The overclocking guide was good, but the benchmarks are hard to figure out, since memory speed and cpu speed are getting higher at the same time.kmmatney - Tuesday, November 20, 2007 - link
OK, figured it out - we just need to compare the Asus P5E3 scores versus the Asus Maximums scores at (8 X 465) to see how much DDR3 improves things over DDR2. Seems to be 1%-5%. Yawn...TA152H - Tuesday, November 20, 2007 - link
When I read the article for the x48, I mentioned that it made no sense for the three chipsets unless the x48 was DDR3 only. Well, I have found out from another site that it will be DDR3 only.That makes the x38 really only useful as a DDR2 chipset, after the x48 is available. This assumes Intel did the right thing of course, and all the ugly overhead for DDR2 is removed from the x48. But if it is, you'd have to be a fool to buy the x38 with DDR3, since it is second best, and has overhead from a function that will not be present on the motherboard. It will give you more heat, and more power use for something that is completely useless. I didn't like Intel including both, but I guess it was to transition to DDR3, so it was a necessary evil until the x48 comes out.
retrospooty - Friday, November 23, 2007 - link
actually, that isnt true. X48 is just an X38 selected out of speed bin to be the fastest. They were going to market it as only DDR3 (that was a marketing decision not a functionality decision) but have since changed their minds.http://www.fudzilla.com/index.php?option=com_conte...">http://www.fudzilla.com/index.php?optio...amp;task...
Either way your arguments are pretty one sided. Even with DDR3 highly overclocked to 2ghz its really only a slight bit faster then DDR2. In fact DDR2 at 1000mhz 4-4-4 beats DDR3 at 2000mhz @ 9-9-9 in most real world tests and apps. Intel is currently going with tri-channel DDR3 on the next gen CPU (nehalem) with internal memory controller. Then and ONLY then is DDR3 going to be worthwhile, and even then its only worthwhile because Nehalem chipsets wont support DDR2. DDR3 is a minor speed bump not worthy of spending money on until Nehalem comes out.