AMD Athlon 4 - The Palomino is Here

Data Prefetch

The Athlon 4's L1 and L2 cache sizes and mapping remain unchanged. As a refresher, the Athlon 4 has a 2-way set associative 64KB L1 instruction cache and a similarly associative 64KB L1 data cache. The Athlon's L2 cache is a 16-way set associative exclusive 256KB L2 cache. The fact that it is an exclusive architecture means that the L1 addresses are not duplicated in the L2 cache allowing AMD to claim a total on-die cache of 384KB for the Athlon 4. That part of the equation remains unchanged, what did change was that the Athlon 4 now has an automatic data prefetch mechanism that works alongside its cache.

This is similar to the Pentium 4's hardware prefetch which predicts what data it will need before it is requested and fetches it from main memory into its cache. This process obviously increases FSB and memory bandwidth usage and it does tend to show more of a performance improvement on higher clocked/higher bandwidth FSB/memory platforms. This does translate into DDR SDRAM being much more useful for the Athlon 4 than it was on the Athlon (Thunderbird).

The data prefetch that is now a part of the Athlon 4's core has actually been around for quite a while with desktop microprocessors. The Athlon 4's data prefetch is simply an evolution of previous prefetch designs. The data prefetch functions can also be software initiated which will take precedence over the Athlon 4's own data prefetch mechanism.

This is where the bulk of the Athlon 4's performance increase does come from and while it isn't an incredible boost in performance, it is respectable nonetheless.