3D Packaging
The reports about an insufficient supply of compute GPUs used for artificial intelligence (AI) and high-performance computing (HPC) servers became common in recent months as demand for GPUs to power generative AI applications exploded. TSMC admits that the biggest compute GPU supply bottleneck is its chip-on-wafer-on-substrate (CoWoS) packaging capacity, as it is used by virtually everyone in the AI and HPC business. The company is expanding CoWoS capacity but believes that its shortage will persist for 1.5 years. "It is not the shortage of AI chips," said Mark Liu, the chairman of TSMC, in a conversation with Nikkei. "It is the shortage of our CoWoS capacity. […] Currently, we cannot fulfill 100% of our customers' needs, but we try to support about 80%. We think...
As HPC Chip Sizes Grow, So Does the Need For 1kW+ Chip Cooling
One trend in the high performance computing (HPC) space that is becoming increasingly clear is that power consumption per chip and per rack unit is not going to stop...
40 by Anton Shilov on 6/27/2022_carousel.jpg)
Intel Accelerated Webcast on July 26th: Update on Process Technology and Roadmaps
Earlier this year, new Intel CEO Pat Gelsinger outlined his new ‘IDM 2.0’ vision for Intel. This vision was a three pronged strategy based on improving its own process...
32 by Dr. Ian Cutress on 7/12/2021
3DFabric: The Home for TSMC’s 2.5D and 3D Stacking Roadmap
Interposers. EMIB. Foveros. Die-to-die stacking. ODI. AIB.TSVs. All these words and acronyms have one overriding feature – they are all involved in how two bits of silicon physically connect...
9 by Dr. Ian Cutress on 9/2/2020_carousel.jpg)
Intel Next-Gen 10-micron Stacking: Going 3D Beyond Foveros
One of the issues facing next-generation 3D stacking of chips is how to increase the density of the die-to-die interface. More connections means better data throughput, reducing latency and...
32 by Dr. Ian Cutress on 8/14/2020
Samsung Announces "X-Cube" 3D TSV SRAM-Logic Die Stacking Technology
Yesterday, Samsung Electronics had announced a new 3D IC packaging technology called eXtended-Cube, or “X-Cube”, allowing chip-stacking of SRAM dies on top of a base logic die through TSVs. Current...
21 by Andrei Frumusanu on 8/14/2020
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