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  • Terry_Craig - Tuesday, May 21, 2024 - link

    I don't understand the logic of this product... I could just use the 7950X instead...
  • shing3232 - Tuesday, May 21, 2024 - link

    For enterprise user
  • Threska - Tuesday, May 21, 2024 - link

    Price mainly. EPYC even on the low-end as been pricey, hence the Ryzens.
  • questionlp - Tuesday, May 21, 2024 - link

    Two key reasons: official BMC support and official server OS support. Even if it's not for a typical Enterprise customer, there are smaller shops that need to run specialized software that will only certify server hardware (see VMware, Oracle, etc.).

    The difference here is that Intel's entry level Xeons lose out on their E cores due to VMware doesn't support hybrid chip configurations and end up being worse deals for those that need basic but certified hardware.
  • PeachNCream - Tuesday, May 21, 2024 - link

    Epyc also has no E cores.
  • pthariensflame - Tuesday, May 21, 2024 - link

    Yes? AMD doesn't make any E-cores. (And if you'd dispute that and call Zen 4c an "E-core", then EPYC *does* have them, in Bergamo and Siena.)
  • alpha754293 - Wednesday, May 22, 2024 - link

    Watch the video from Patrick Kennedy from ServeTheHome. https://www.youtube.com/watch?v=JokLRV6KLeE

    He answers this question explicitly.
  • Kevin G - Tuesday, May 21, 2024 - link

    I was hoping for a model with 192 MB of aggregate of L3 cache with these models. The dual CCD but only one with 3D V-cache is an odd configuration. There is a case for a 'best of both worlds' philosophy here between cache and clock speeds but tuning where applications run for best performance is necessary (core parking etc.). A slightly lower clocked, 16 core, 192 MB of L3 cache model would provide some simplification for deployments.

    While unlikely but would've been nice is to have is the single CCD models (those 8 cores and below) have a new interposer that leverages two Infinity Fabric links to the CCD. The Zen 4 CCD designs support dual links to the IO die but AMD has not deployed any models actually leveraging this which would provide a nice bandwidth boost. This would give these chips an edge for some workloads vs. their earlier consumer counterparts.
  • cp0x - Sunday, May 26, 2024 - link

    They definitely needed to include the 7800x3d equiv if they didn't pull off the trick you're suggesting ...
  • FWhitTrampoline - Tuesday, May 21, 2024 - link

    "Since these are all based on AMD’s consumer discrete CPUs, the underlying architecture in all of these chips is Zen 4 throughout."

    The CCDs for All Epyc/Ryzen generational products come from the same CCD diffusion lines and are just binned for performance metrics, and so the cream of the crop CCD samples goes into Epyc/TR Pro while Ryzen gets the leakier CCDs that may require more voltage to operate stably! To my understanding most of the I/O differentiation between Epyc/Ryzen happens at the I/O die level with only minimal CCD features disabled.

    Does each Epyc bound CCD get 2 Infinity fabric links per CCD enabled to the I/O Die whereas for Ryzen only one of the 2 IF Links to the I/O die per CCD is enabled? And there is no RDIMM supported on these SKUs?

    And as far as the V-cache do the Epyc parts not have options for both CCDs to have V-Cache stacked on top? Is the I/O die utilized here not having some extra features enabled that is not for any consumer variant if there's some extra IP that's not mentioned by AMD but is there for special use cases?

  • Scabies - Tuesday, May 21, 2024 - link

    I feel like I'm taking crazy pills- you say 28 PCIe lanes is an expected feature, but 7000 series Ryzen processors only have 24. Thus, despite the socket being the "same" AM5, I doubt motherboard and processor cross compatibility will be a thing. Plus we're probably looking at a different IO die.
  • Ryan Smith - Tuesday, May 21, 2024 - link

    Consumer Ryzens will always come with a chipset (I/O Hub). So there's never more than 24 lanes free for general I/O.

    EPYC 4004 can potentially come without a chipset, so long as the server vendor doesn't need the extra I/O.

    https://images.anandtech.com/doci/17585/SoC_26.png
  • Xajel - Saturday, May 25, 2024 - link

    28 PCIe lanes true, but only 24 lanes are exposed to the user, the extra 4 lanes are used to connects the CPU to the chipset, which was always the case (even with AM4, which had less lanes)
  • nandnandnand - Tuesday, May 21, 2024 - link

    They did the 4124P dirty, only 16 MB L3 cache.

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